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Abstract                 Volume:4  Issue-7  Year-2016          Original Research Articles


Online ISSN : 2347 - 3215
Issues : 12 per year
Publisher : Excellent Publishers
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Advanced Level Modelling and Simulation of CAN Controller for its Implementation in FPGA (SoC) with Synthesis and Timing Results for Integrated CAN Node
Duhita B. Paratane1*, A.M. Patil2 and Jitendra P. Chaudhari3
1,2M.E. Electronics and Telecommunication, J.T. Mahajan College of Engineering, Faizpur, India
3Charusat Space Rsearch and Technology Center, Charotor University of Science and Technology, Changa, Anand, Gujrat, India
*Corresponding author
Abstract:

Conventional CAN controller is integrated in the SoC (FPGA + Hard Processor) Chip. The CAN protocol functionality is implemented in the FPGA fabric along with block memory utilisation as buffers and is controlled by ARM Processor (Hard Processor System) present in the same chip (Duhita et al., 2016). The CAN controller has been designed using Verilog so it can be targeted with different implementation technologies in custom designs. In this paper the synthesis and timing results of the implemented integrated CAN controller are discussed. The MAC (medium access Control) Sub-layer is designed separately using Verilog HDL and synthesized in FPGA programmable fabric of the SoC Chip. MAC layer i.e. CAN controller logic utilisation and timings along with timing constraints are discussed here. Control and application part of the CAN module is done in hard processor system (HPS) Cortex A9 microprocessor. The HSP system’s specifications are also given in this paper.  The CAN controller module is designed using Quartus Prime Lite software in Cyclone V SoC “5CSEMA5F31C6N” device. 

Keywords: Synthesis, Placement and Routing, Timing constraints, RTL (Register Transfer logic), CAN (Controller area Network) controller, CAN node, FPGA, SoC, HPS, Verilog Modules.
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How to cite this article:

Duhita B. Paratane, A.M. Patil, Jitendra P. Chaudhari. 2016. Advanced Level Modelling and Simulation of CAN Controller for its Implementation in FPGA (SoC) with Synthesis and Timing Results for Integrated CAN NodeInt.J.Curr.Res.Aca.Rev. 4(7): 76-88
doi: http://dx.doi.org/10.20546/ijcrar.2016.407.010